Product Description

This single–width CAMAC module is a high speed ACB Auxiliary Controller which performs a list of commands held in an Instruction Store. The module contains a Data Store with separate Read and Write Pointers for sending and receiving CAMAC data.

Features

• Enhanced version of successful LP1340.
• Up to 256K x 24 bit words Data Memory.
• 8K x 16 bit words Instruction Store.
• Battery backup on BOTH Stores.
• EEPROM compatible Instruction Store.
• Seven Front Panel Trigger inputs, each leading to a different set of Instructions via a ”Bootstrap” jump table. Data tagging by reading the Instruction Pointer on entry.
• Conditional Jump - List execution can now be controlled by testing the state of Q from the last command or by a mathematical compare on the last Read Data:-

  • Jump unconditionally.
  • Jump if no Q response.
  • Jump and Await Trigger.
  • Jump if Greater Than.
  • Jump if Less Than.
  • Jump if Equal To.

• Self Trigger - Internal clock triggers at 100m S or 1 mS rate.

Instruction Store

The Instruction Store holds 8192 words of 16 bits, N.A.F. format, with a 13-bit auto-incrementing pointer. The store and pointer are fully read/writeable and the Processor can be started at any position in the list. Special code instructions in the list, using spare bits, allow execution to be terminated or branched to a specified address (in the bottom 2K), and to continue immediately or to await a trigger. This conditional branching can either proceed until a STOP instruction is encountered or some other stop condition occurs (eg. Pointer Overflow, no Q timeout).

Data Store

The Data Store is 128K/256K words of 24 bits battery backed with two independent 18 bit auto–incrementing Read and Write Pointers, both are able to cover the entire store area. The Store and Pointers are fully Read/Writeable. Steady incrementing of Pointers occurs during the List Execution, even during branching or repeated execution of the same list of commands. The selection by the current instruction of Read or Write (or neither) Data Pointer is done automatically using F16 and F8.

Starting

The module powers up ”unbooked” and is booked by F(27)A(0). The Q response to this command is ’0’ if the unit has already been booked, which ensures that only one computer can access the module at a time. Once in the booked state, the internal Stores and Pointers are prepared and the processor is started by either a dataway command – set GO bit in the LAM Status Register – or by one of seven external triggers or a link selected LAM if triggering is enabled. Execution then proceeds at approaching maximum Dataway rate until a STOP condition is met. Three front panel LEDs show which Trigger Input is currently active.

Stopping

The List Processor will normally continue to perform instructions in sequence until it reaches one with Bit 16=1, which causes it to STOP if Bit 15=0, generating a Finished LAM or Branch (Bit 15=1) to another set of commands whose start address is specified by Bits 1 to 11. From there it will either continue or Await Trigger depending on Bit 14 in the Branch Instruction (0=continue, 1=wait).

The LAM Status Register shows the four main Status bits: GO bit 4, FINISHED bit 3, NO Q bit 2 and NO X bit 1.

Each instruction requires X to be present, but may ignore Q (if bit 15=1) or loop on Q for up to 10uSec, whereupon it will abort and set NO Q LAM. Other causes of such a timeout, eg ACB busy or stuck, will cause the same abort.

The front panel STOP input is dual purpose and can be link selected to be a VETO input, which when pulled LOW at S2 time makes the LP1341 ignore the data by not incrementing the relevant pointer. Absence of Q has the same effect.

Recommended Access

It is strongly recommanded that once the List Processor has been put into the GO or Await Trigger Mode, the commands issued to it should be restricted to READ or TEST commands so as to avoid pointer corruption etc.