Hytec Electronics Ltd

1375 - CAMAC SHARC DSP IP CARRIER/CONTROLLER.

Introduction.

This double-width card is designed to fit into a standard CAMAC crate and house up to four Industry Pack (IP) cards. An on-board DSP processor, an Analogue Devices ADSP21061, has access to these industry packs and to a dual-port memory visible through the CAMAC port. The DSP processor has two 1M x 8 Flash EPROM devices from which to boot, 256K x 32 bits of local fast SRAM, a 16550 UART RS232 front panel port and two SHARC serial ports, also on front panel connectors. The DSP processor can also access the CAMAC crate through an ACB Auxiliary Controller function built into the unit.

Hardware Details.

The arrangement of the DSP processor and its peripherals is almost identical to that used in the Hytec 8003.2 VME64x SHARC DSP board – in fact the memory map as seen from the SHARC processor is the same except for the addition of the dual-port RAM and the CAMAC master interface. The DSP processor is designed to boot from either of the two Flash EPROMs depending on a mode selection jumper. It can also be operated remotely through a JTAG diagnostic port. Further, it can, with suitable firmware, boot itself or download code via the front panel RS232 port. When the DSP processor is running, the normal mode of communication with an external CAMAC host will be through the dual-port RAM. This is because of the synchronous nature of the CAMAC bus and the inability to guarantee granting of ownership of the SHARC bus to CAMAC within 400 nanoseconds if the DSP is busy.

The CAMAC port is constructed using a Xilinx FPGA device which decodes all CAMAC commands addressed to this module and responds to addressed accesses from the SHARC by executing the selected CAMAC Master function. Control and Status registers within the Xilinx allow CAMAC to control and observe the DSP processor and vice-versa.

A full hardware list of the card is as follows:

32MHz ADSP 21061 DSP Processor

2 x 1M x 8 90 nanosecond Flash EPROM devices.

2 x 256K x 16 20 nanosecond SRAM devices.

DS16550 UART device with RS232 interface.

4 x IP locations with I/O ports connected to front panel SCSI-II 50-way connectors equivalent to those on the transition cards of the 8000 series VME64x cards.

32K x 24 bits dual-ported RAM between CAMAC and DSP.

Full CAMAC ACB Master and slave interface in R/G mode with front panel LEMO connectors.

Software Details – the SHARC Memory Map.

The way that the SHARC processor addresses external devices is on the basis of banks. Each bank has a chip select line associated with it and a register, which defines how cycles are completed. The four select lines are connected as follows:

MS0 or BMS (Boot memory select) connects to flash memory 0 or 1 (chosen by the Xilinx).

MS1 connects to the PC16550 UART device.

MS2 connects to the external RAM

MS3 connects to the Xilinx for access to Xilinx internal registers, the dual-port RAM, the CAMAC Master interface and the IP cards.

Software Details – the SHARC Memory Map. (cont.)

All except MS3 should have their cycles completed internally by the wait state machine. The default value of 6 internal clocks (of the 32MHz master clock) is OK for all these devices. Cycles to the Xilinx (and to the IP cards through the Xilinx) should be terminated externally by ACK after an internal wait of 6 clocks.

The actual access times of the external devices, are as follows and the user may trim the wait state machine to these timings if desired:

Flash EPROM: 90 nanoseconds.

SRAM: 20 nanoseconds

PC16550 UART: 150 nanoseconds approx. (use 6 wait states).

SHARC Address Map:

Address Range Contents

00000000-0007FFFF SHARC Internal RAM

00080000-003FFFFF SHARC multi-processor space (not used).

00400000-004FFFFF Flash EPROM 0.

00500000-005FFFFF Flash EPROM 1.

00600000-00BFFFFF Aliases of Flash EPROM’s 0 and 1.

00C00000-013FFFFF PC16550 UART Device – only a very small part used!

01400000-014FFFFF 256K X 32-bits External RAM.

01500000-01BFFFFF Aliases of external RAM.

01C00000-01C007FF IP I/O and ID access plus Xilinx registers.

01D00000-01DFFFFF Dual-Port RAM – 32K x 24 bits.

01E00000-01EFFFFF CAMAC Master access in FNA format; F16 from R/W.

02000000-020FFFFF IP ‘A’ Memory access (1M 16-bit words).

02100000-021FFFFF IP ‘B’ Memory access.

02200000-022FFFFF IP ‘C’ Memory access.

02300000-023FFFFF IP ‘D’ Memory access.

Thus each of MS0, 1, 2 and 3 MUST to be set up as 8M blocks.

The Xilinx provides ACK termination for all accesses by MS3, whether the SHARC addresses internal registers, configuration data, dual-ported RAM or IP cards. It also provides termination even if the addressed device is not present (that is an absent or faulty IP card).

CAMAC Master Port Addressing.

Address decoding within the Xilinx detects CAMAC Master Port cycles and arbitrates for the ACB in the usual way. The SHARC address is used in the following way:

A31-A20 must equal HEX 01E and MS3 must be present. The rest of the address is passed to the CAMAC port as follows:

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Z C F8 F4 F2 F1 EN16 EN8 EN4 EN2 EN1 A8 A4 A2 A1

The CAMAC line F16 is derived from the DSP processor’s write line and is asserted accordingly. The presence of a ‘1’ in either ‘Z’ or ‘C’ bit positions produces the appropriate Z or C cycle and ignores the rest of the command address.

SHARC XILINX Registers.

The ADSP21061/2 has its own set of registers in the Xilinx through which its operation is controlled either by CAMAC or the 21061. The set is positioned at an offset from the base address for IP I/O etc., 0x01C00000, and comprises the following:

Offset	Register	Description
0x420	IP Status	Allows state of IP INT and Error flags to be monitored
0x428	Control & Status Register SH	Set up of SHARC part of 8003
0x42C	IP Interrupt Select	Selects IP interrupts to be mapped to SHARC IRQ

8003 SHARC Registers

IP Status Register (R/W)

Address: Read = Base + 0x0420

D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

DSP IP ERR.

ERR

INT REQ D1

INT REQ C1

INT REQ B1

INT REQ A1

INT REQ D0

INT REQ C0

INT REQ B0

INT REQ A0

Two interrupt status and one error status bits for each of IP sites A – D. Plus a flag bit, bit 12, indicating a failure when the SHARC attempted an IP access. Any write to offset 0x420 clears this bit.

Control & Status Register SHARC (CSR SH)

Address: Base + 0x0428

D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

FLAG3

FLAG2

FLAG1

FLAG0

OE-F2/3

OE-F0/1

IPMS1

IPMS0

J22

IRQ1

IRQ0

J14

J13

RST

RST: Reset the SHARC processor (pulse on write ‘1’) reads ‘1’ for SHARC RUN enable.

J13/14 State of start-up jumpers, read only (RO): jumper OUT = ‘1’.

IRQ0 ‘1’ = map selected IP interrupts to SHARC IRQ0. (R/W)

IRQ1 ‘1’ = map selected IP interrupts to SHARC IRQ1. (R/W)

[Select only one of these!].

J22 State of the write protect jumper, read only (RO): jumper OUT = ‘1’ = Write Enabled.

IPMS0, 1 Reflects state of IP memory size selection from CSRCB. (RO).

Z ‘1’ = Permit CAMAC Z cycle to reset SHARC processor. (R/W).

OE-F0/1 Output enable for Flag0 and Flag1 outputs.

OE-F2/3 Output enable for Flag2 and Flag3 outputs.

Flag0 Writeable bit which, if enabled, will drive the SHARC Flag0 pin. Reads actual state.

Flag1 Writeable bit which, if enabled, will drive the SHARC Flag1 pin. Reads actual state.

Flag2 Writeable bit which, if enabled, will drive the SHARC Flag2 pin. Reads actual state.

Flag3 Writeable bit which, if enabled, will drive the SHARC Flag3 pin. Reads actual state.

IP Interrupt Select Register (Read/Write)

Address: Base + 0x042C

D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

SHARC IP ERROR

IPINT D1

IPINT C1

IPINT B1

IPINT A1

IPINT

IPINT B0

IPINT A0

This selects which IP interrupt lines will be mapped to the SHARC IRQ line selected in CSR SH. Note that it would be incorrect to map an IP interrupt to both CAMAC and SHARC. It also allows the SHARC IP ERROR bit to be mapped to the SHARC IRQ.

‘1’ = corresponding IP card interrupt enabled.

The CAMAC Slave Port.

The best way to understand how the card is controlled and monitored from CAMAC is by reviewing the proposed command set:

Command Function X Q

F(0) A(0) Read Dual Port RAM at the selected address (increment ptr.) 1 1

F(1) A(0) Read Dual Port RAM address pointer 1 0

F(1) A(12) Read LAM Status Register 1 0

F(1) A(13) Read LAM Mask Register 1 0

F(1) A(14) Read LAM Request Register 1 0

F(8) A(15) Test LAM 1 LAM

F(16) A(0) Write Dual Port RAM at the selected address (increment ptr.) 1 1

F(17) A(0) Write Dual Port RAM address pointer 1 0

F(19) A(13) Selective set LAM Mask Register 1 0

F(23) A(13) Selective clear LAM Mask Register 1 0

The LAM status and mask registers correspond to the IP status register shown above. Bits which are set to ‘1’ in both registers will give rise to corresponding bits in the LAM Request register and also set LAM.

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