|
Hytec Electronics Ltd. |
|
CAMAC SMC 2404 STEPPER MOTOR CONTROLLER Product Description
This module is a single–width CAMAC unit, containing four independent channels of motor control electronics. It is similar to the earlier SMC1604 (catalogue number 256) but with three paticular improvements: 24–bit step magnitude instead of 16; programmable speed and ramp rate; and the ability to accept shaft–encoder feedback inputs for closed loop positioning. Each channel uses 6 bits of a common 24–bit Control and Status Register for start/stop, limit switch and drive system fault functions. There is a corresponding Mask Register and a Request Register, making up a standard LAM register set. Each channel then has a 24–bit Step Count Register (up to 16 million steps per movement); a 16–bit ’Profile’ Register to control speed, speed multiplier, ramp time, direction of movement and opto–encoder selection, and a 16–bit Slow–Down Count Register for defining the point at which the ramp down should start, based on the chosen high speed and ramp time. Functional Description On the front panel there are four 15–way Cannon socket connectors, one for each channel. Each is connected to the relevant drive system electronics for step and direction outputs (opto–isolated), limit switch (contact closure) and fault (opto–isolated) inputs and optional quadrature encloder signals (differential RS485). With these connected, the channel can be operated and the motor moved. Associated with each channel connector is an LED, which flashes when the motor is stepping. 
|
Profile Register Format
The slow–down count number corresponds to the top 16 bits of the 24–bit step count register at the point where the slow–down to start/stop speed should commence, evaluated by the host computer from the speeds and ramp time.
Control and Status Register
This is at subaddress 12 and is read with F(1), selectively set with F(19) and selec-tively cleared with F(23) by setting corresponding write lines to specify which bits to set/clear or leave unchanged. Each channel has 6 bits in the CSR, corresponding to the five bits in the SMC1604 CSR, with a new extra bit called ’abort’. Channel 1 uses bits 1-6, channel 2 uses bits 7-12, channel 3 uses bits 13-18 and channel 4 uses bits 19-24. The function of each of the 6 bits per channel is as follows:-
Note: when you read the GO/RUN bit, even if you have reset the GO bit to perform a ’soft stop’ the bit will still be set to show you that the channel is slowing down.
Bits 1 to 4 in each section of the CSR have corresponding LAM Mask Register bits at subaddress 13, read by F(1), selective set with F(19), selective clear with F(23).
The logical AND of CSR and Mask (known as the Request Register) can be read at subaddress 14 with F(1) and any bits present in this register will cause the module to generate LAM.
| Hytec Electronics Ltd Post : 5 Cradock Road, Reading, Berkshire, RG2 0JT, England. Phone : +44 (0)118 9757770 Fax : +44 (0)118 9757566 Email : sales@hytec-electronics.co.uk |