Product Description

The ADC 505LCJ is a single–width differential 12–bit ADC with a speed of 35usec/sample with fast sample/hold and no missing codes between 0 o C and 60 o C. It has three modes of operation; mode 0 or continuous scan, where all channels are converted in sequence at a rate selected by 4–bit switch from 50uSto 125uS, and thus the results loaded in memory; mode 2 or single rigger (one channel converted and the address incremented each time a trigger or F(25)A(0) is received); and mode 3 or scan trigger (one single scan of all channels in sequence at selected rate when trigger of F(25)A(0) is received, followed by LAM if enabled). Mode 1 is for testing – conversions are disabled and data may be written to the 16 x 24–bit memory and read back. Mode selection makes checking/testing and DMA sequencing very easy. The input impedance is normally set to 100M ohms, and over–voltages when powered of +/-32Vdc, and transients to 300V, can safely be withstood. Switched gain is available; standard settings are x1, x10, x100 and x1000 but other values can be factory–set on request. Common mode rejection for dc–60Hz at the stated gains are x1, 74dB; x10, 94dB; x 100, 104dB. Input is via a front–panel 37–way D connector and ranges are 0-5V, 0-10V and +/-10V.

The 506LCJ is identical to the 505LCJ except it has 32 inputs (two 37D connectors) instead of 16.

The 508LC–8 is similar to the 506LCJ but is 14–bit instead of 12–bit, and the standard gain settings are x1, x2, x10 and x 100. The corresponding speed settings are 50uS, 55uS and 65uS; there is also a slower speed setting of 120S which may be used at any gain. Various range settings are available, from 0–5V to +/–10V, and various codes are available too. Like the 506 unit, data may be directly written to and read back from the 32 x 24–bit memory. In addition to the ADC chip there is a separate window discriminator for out–of range warning. The input is by two 50D front–panel plugs, allowing 16 TTL inputs as well as the 32 analogue inputs.

ADC Read Data Format (24-bit)

Analog signals are brought in via a front panel by two 25, 37 or 50 way D type connectors as shown on front panel drawing (left). The CMOS Multiplexers have a very high input impedance, this is set by resistor at value of 100M Ohms. Overvoltage of up to +/–32V dc continuous (if powered; otherwise +/–20V dc) or transients of up to 300V can safely be withstood.

Switched gain is available, with a binary–coded switch pair to give X1(code 00), X10(code 01), X100(code 10), X1000(code 11), other gain values can be factory set on request. Common mode rejection DC 60Hz: X1=74dbs, X10=94dbs, X100=104dbs.

Link set ranges are 0-5V, 0-10V, +5V and +10V; since this is truly differential, polarity reversal is simply by on-board switch.

A separate window discriminator allows Q=1 on reading data only if input voltage is within preset limits, normally set to 2 bits outside the input range selected. This is an important system safeguard. Not fitted on the LCJ version. Replaced by simple range switching.