IP-DAC-8402-L 16-CHANNEL DAC INDUSTRY PACK

Product Description

The Hytec IP-DAC-8402-L is a single-width Industry Pack that provides 16 channels of simultaneously updated digital to analogue conversion with the following characteristics:-

• 16 independently programmed channels
• Full 16 bits resolution
• Single offset and full-scale trims
• Low offset error - +/-0.5mV typical
• Low gain error - +/-5LSBs typical
• Low error drift - 2ppm per deg C
• +/-5V full scale output
• +/- 10mA current drive capability with continuous short-circuit protection
• Drives capacitive loads to 10000pF
• Straight Binary Code
• 10KHz update rate
• Simultaneous up-date Power-on disable (outputs set to 0V)
• System to plant isolation to 100V when externally powered
• Serial number, PCB and firmware issue stored on-board
  
• Software Drivers are available including EPICS drivers.

Specifications

Operating Modes

There are two operating modes:-

1. Registered - the DAC ouputs are controlled by the contents .
2. Memory - the outputs are updated for the programmed number of samples at the programmed clock rate.

Memory Map

There are two main buffer memories of 512k updates each (lower and upper buffers). These are each divided into sixteen segments allocated to updates for DAC1 to DAC16. When DAC16 has been updated from the top of the lower buffer, the Half Full Flag status is set and when it has been updated from the top of the upper memory buffer the Full Flag status is set.

Application Registers

There are twenty application specific (I/O) registers; the CSR, the number of samples per trigger, the conversion pointer, the clock rate and the DAC transparent update registers.

CSR

Buffer Memory Pointer Base Address

The current conversion address is given by the conversion base address offset by the DAC number and the Half Full status. The buffer pointer base address is the number of updates output.

Number of updates

The number of updates register allows the number of updates per trigger to be programmed. If the memory buffer size is exceeded the update values will wrap around from the upper memory to the base of the lower memory.

Clock Rate

The clock rate register is a four bit register which enables codes 0 - 12 to enable frequencies of 1 Hz to 10kHz in multiples of 1,2,5 or 10. (E.g. 0=1Hz, 1=2Hz, 2=5Hz, 3=10Hz and so on) Each clock pulse will initiate 16 DAC updates from memory.

DAC Update Registers

The 16 DACs are updated by these registers whenever they are overwritten and the EX bit is zero.

Vector Register

The interrupt vector is stored in a 16 bit register.

ID PROM

The ID data is stored in a serial EEPROM. The byte addresses are as below:-

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Last modified: July 27, 2005