The Hytec IP-DAC-8404 is a single-width Industry Pack that provides 16 channels of simultaneously updated digital to analogue conversion with the following characteristics:-

• 16 independently programmed channels
• 5 programmable ranges per channel 5V, 10V +/-5V, +/-10V, and +/-2.5V
• 16 bits resolution
• 64K samples per channel memory.
• Registered or memory fetch updates.
• Two independent digitally controlled full-scale trims for each group of eight channels.
• Low offset error - +/-5mV typical (With software Cal applied +/-0.5mV)
• Low gain error - +/-5LSBs typical (With software Cal applied +/-2.5LSBs typ.+/-4.5LSBs max)
• Low error drift - 2ppm per deg C
• +/- 10mA current drive capability with continuous short-circuit protection
• Straight binary code
• 10KHz update rate
• Power-On Reset to 0V
• 100V system to plant isolation when externally powered
• Board serial number, PCB issue and firmware version held on ROM.
• External Triggering
• Continuous function generation.
• Internal/External update clock rates
• Internal update clock rates programmable (10KHz,5KHz,2KHz,1KHz,500Hz,200Hz,100Hz,50Hz,20Hz,10Hz,5Hz,2Hz and 1Hz)
• Pin-out and software compatible with DAC8402 (in command default mode).

Product Specifications

Size: Single width Industry Pack 1.8ins x 3.9 ins
Operating temp: 0 to 45 deg C ambient
Number of channels: 16
DAC resolution: 16 bits
Data format: 16 bits binary
Range: Programmable 5V, 10V +/-5V, +/-10V, and +/-2.5V
Output current: +/-10mA @ FS
Capacitive load: Stable up to 2000pF
Short circuit duration: Continuous
OverV withstand: No internal protection from external voltages provided
Update rate: 10KHz max
Power: +5V @ 300mA typical
+/-12V @ 120mA typical when switched to internal
Isolation: 100V via opto-isolators (if externally powered)
Integral non-linearity: +/-1LSB max
Diff non-linearity: +/-1LSB max
Offset error: +/-200uV max
Gain drift: 3ppm per deg C
Gain error: +/-5LSBs typ. +/-16LSBs max.
Output slew rate: +/-13V/us min.
Settling time: 20us max.to 0.005% of final value for 1000pF load capacitance

Operating Modes

There are two operating modes:-
1. Registered – the DAC outputs are controlled by the contents of the DAC registers.
2. Memory – the outputs are updated for the programmed number of samples at the programmed clock rate.
All the outputs are updated serially but change together (there will be slight changes due to differences in the slew rate of the amplifiers (about +/-1uS) at the end of an internal update cycle.
The outputs may be updated at a rate of up to 10KHz. The two methods to update the 8404 DACs are detailed below.

Using Registers to update DACs

There are 16 individual DACs on the IP Card with 16 Data & Command DAC registers to access each one. This allows the user to set if required each DAC to different voltage ranges. The DACs are serially loaded with a 32 bit data stream comprising of the first 16 bits with the command word, to set the required voltage range, and the last 16 bits correspond to the data to set the output of the DAC to. Therefore, both the data and command registers must both be set the DACs to operate correctly.

The DACs are arranged in two groups, DACs 1 to 8 are daisy chained together to form bank A and DACs 9 to 16 daisy chained to form bank B.

Once the registers have been loaded, the module can then be ARMed and the data from the registers will be serially loaded from one DAC to the next until all the data has been passed to all of the DACs. At this point the DAC outputs are automatically updated giving 16 simultaneous outputs. While the unit is ARMed the DACs are constantly refreshed with the contents of the registers which can be changed during this time. There is a delay which is fixed of approximately 32us after ARM is set, before all the outputs change together.


Using Memory to update DACs

In this mode the data to be sent to the DACs is loaded from memory instead of the DAC Data register, however the command for each DAC is still required, but only has to be set once at the start. Once the DAC Command has been set this remains unchanged, unless the voltage range is changed, then the new command must be written again.

The onboard memory is first loaded with the required data and the number of memory locations used is entered in to the Number of Updates (NCO) register. With the DAC Command Register already written and set, the Control and Status Register (CSR) is then set to enable memory updates and ARM to unit with a software command. A trigger can then be issued either by a software command or by an external trigger to start down loading the data held in memory to the DACs via the registers as detail above. In this mode the registers are updated with new data from the memory at the update clock rate which is derived either internally or externally. The memory address is automatically incremented.

When the programmed number of output has occurred the unit will stop and generate an interrupt if enabled or if set in continues mode the address counter will be zeroed and the output repeated (no interrupt generated in continues mode) until the ARM bit is cleared or the continues bit CC in the CSR is cleared.

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