Hytec Electronics Ltd

Data Acquisition and Control

Industry Pack IP-ADC-8408
 ADC 16 channel 12 bit

Description

The Hytec IP-ADC-8408 is an Industry Pack that provides 16 channels of 
simultaneously sampled analogue digitisation with the following characteristics:-

•	16 independently programmed channels
•	12 bits resolution
•	Single full-scale and offset trim.
•	Differential inputs provided by on-board instrumentation amplifiers for each channel.
•	0V to 5V unipolar full-scale standard and +/-2.5V bipolar by jumper option.
•	System gain can be factory adjusted for 0V to 10V and +/-5V full scale input.
•	Front-end instrumentation amplifiers can be factory set for gains of up to x1000.
•	High common mode rejection (120dB).
•	Input over-voltage protection to +/-40V.
•	FIFO memories for single sample and optional triggered sample readout
•	Calibration factors stored in PROM.
•	Low offset error - +/- 5mV max (un-calibrated), +/-1mV (calibrated)
•	Low gain error - +/- 5mV full scale (un-calibrated), +/-1mV (calibrated).
•	Low error drift  -  10ppm per deg C
•	Code format:  000h  = 0V and FFFh = +5V  Standard.
•	Code format:  000h  = 0V and FFFh = +10V  Variation ‘U’.
•	High input impedance – 5Gohms.
•	Up to 100KHz sampling rate 
•	Simultaneous sampling – 1us acquisition time
•	System to plant isolation to 100V when externally powered by DC/DC converter option
•	Serial number, PCB issue and firmware issue held in ID PROM
•	32MHz IP system clock operation (8MHz optional).
•	10MHz Clock signal for synchronising sampling clocks between cards or ‘GO’ signal 
             for synchronising sampling between cards.

2. Overall Specifications
 

Size	Single width Industry Pack 1.8ins x 3.9 ins
Operating temp	0 to 45 deg C ambient
Number of channels	16
ADC resolution	12 bits
Diff. Non-linearity	+/- 1LSB, monotonic
Int. Non-linearity	+/- 2LSBs
Offset error	+/-5mV uncorrected
Offset drift	+/-2ppm per deg C typical
Gain error	+/-5mV uncorrected
Gain drift	+/-2 ppm per deg C typical
Range	+5V full-scale (+ve input referred to –ve input). +/-2.5V optional.
Cross-talk	+/-1LSB channel to channel for FS input on adjacent channel.
CMRR	120dB
CMV	+/-12V
Overvoltage	+/-40V.
Throughput	100KHz max
Acquisition time	1us
Conversion time	6.5us
Bandwidth	20kHz (factory set – other cut-offs can be specified)
SNR	-90dB at 1kHz typical
SINAD	-90dB at 1kHz typical
Isolation	100V via opto-isolators (if externally powered)
Data format	12 bits straight binary
Memory	Buffer register for each conversion and FIFO for all 16
Power	+5V @ 300mA typical; +/-12V @ 200mA typical when switched to internal

Operating Modes

There are three operating modes:-

1. DC sampling – when the unit is armed or receives an External 10MHz signal, the inputs are sampled at the programmed clock rate and the conversions placed in a 16 conversion pre-trigger FIFO. Interrupt or DMA Request is generated when the FIFO is full. The FIFO may be readout as it is filling.

2. Register mode – the last ADC reading may be read at random from each addressed ADC register.

3. Triggered sampling – When the board is triggered conversions are stored in a larger external FIFO which will hold 256 16bit samples for each of the 16 channels. Interrupt or DMA Request is generated when the FIFO is full. The FIFO may be readout as it is filling. Once triggered and FULL the external FIFO remains unchanged until it is read completely. The unit can only be retriggered once the FIFO had been emptied.

 Download full Product Specification in .pdf format.

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Information in this document is subject to change without notice.
Other products and companies referred to herein are trademarks or registered trademarks of their respective companies or mark holders.
Our policy is one of continuous product development and the right is reserved to supply equipment which may vary slightly from that described.

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Last modified: November 10, 2006