Hytec Electronics Ltd

Data Acquisition and Control

Industry Pack
IP-ADC-8413 16 Channels 16 bits

Description

The Hytec IP-ADC-8413 is an Industry Pack that provides 16 channels of simultaneously sampled analogue digitisation with the following characteristics:-

• 16 independent channels (one ADC per input)
• 16 bits resolution – 15 bits no missing codes
• Single full-scale trim for hardware gain adjustment.
• Software calibration by software driver possible using stored offset and gain parameters.
• True full differential inputs.
• +/-10V full-scale standard programmable to +/-5V full-scale resolution all inputs.
• Front-end instrumentation amplifiers can be factory set for gains of up to x1000.
• FIFO memories for single sample and triggered sample readout (256K post-trigger samples)
• Low offset error - +/- 2.5mV without software calibration. (+/-2LSBs after software calibration)
• Low gain error - +/- 0.5% FS without software calibration.(+/-2LSBs after software calibration)
• Low error drift - 2ppm per deg C
• Code format: two’s complement
• High input impedance – 1Gohms.
• Up to 150KHz sampling rate from an external clock (valid only on 32MHz IP clock frequency)
• Simultaneous sampling – 70ns aperture delay time. Uncertainty time and channel matching 3ns.
• System to plant isolation to 100V when externally powered by DC/DC converter option
• Serial number, PCB issue and firmware issue held in ID PROM
• 8/32MHz system clock operation
• EPICs driver support

Overall Specifications

Size: Single width Industry Pack 1.8ins x 3.9 ins
Operating temp: 0 to 45 deg C ambient
Number of channels: 16
ADC resolution: 16 bits
Diff. Non-linearity: Monotonic to 15 bits (at 200kHz throughput)
Int. Non-linearity: +/-2LSBs max.
Offset error: +/-2.5mV uncorrected.
Offset drift: +/-0.5ppm per deg C typical
Gain error: +/-0.5% uncorrected
Gain drift: +/-2 ppm per deg C typical
Range: +/-10V full-scale (+ve input referred to –ve input.
Cross-talk: +/-1LSB channel to channel for FS input on adjacent channel.
CMRR Greater than 80dB
CMV: +/-12V.
Over-voltage: +/-50V.
Throughput: 150 KHz max from an external clock (valid only at 32MHz IP system clock)
Aperture time: 70ns typical (conversion start to hold)
Conversion time: 3us (plus 1.6 us readout to register)
Bandwidth (-3dB): 100kHz (factory set – other cut-offs can be specified)
SNR: -90dB at 1kHz typical
SINAD: -90dB at 1kHz typical
Isolation: 100V via opto-isolators (if externally powered)
Data format: 16 bits two’s complement.
Memory: Buffer register for each ADC conversion and FIFO for all 16 conversions
On-board FIFO: 256K conversion values with half full and full flags
Power: +5V @ 300mA typical, +/-12V @ 200mA typical from VME or 8912.

Operating Modes

There are three operating modes:-

1. Internal FIFO

When set to this mode, the conversions of the last sample are stored into an internal FIFO. To perform this operation the unit must first be armed, (set bit 15 in the CSR), then the inputs are sampled at the programmed clock rate or external clock rate, if selected. The internal FIFO can only store the last sample of all 16 channels; this will then generate an interrupt to indicate the FIFO is full and set the full flag high, F bit 0 CSR register. The FIFO may be readout as it is filling. The FIFO is cleared just before the next sample data is stored, therefore the FIFO only holds the last sampled result.  

The purpose of this FIFO is to increase the speed of communication over IP using block transfer.

 2. Register mode

In this mode the last sampled results of the inputs are stored in the ADC registers when armed, at the programmed clock rate or external clock rate, if selected. The ADC reading may be read at random from each addressed ADC register. Therefore, in this mode the user can chose which channels to monitor instead of all 16.

 3. Triggered sampling

When the board is armed (set bit 15 in the CSR), and either a software or hardware trigger is detected, conversions are then stored in a 256K external FIFO. This FIFO can store up to 16,384 samples of each 16 channels. An interrupt request is generated when the FIFO is full and the full flag will be set TF bit 1 in the CSR register. The FIFO can be readout as it is filling. The data is stored in groups of 16, sample 1 of all 16 channels, then sample 2 of all 16 channels and so on up to sample 16384 of all 16 channels. Therefore, even though the data can be read out of the FIFO at any time, groups of 16 reads should be performed to keep the sample format intact.  

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Information in this document is subject to change without notice.
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Our policy is one of continuous product development and the right is reserved to supply equipment which may vary slightly from that described.

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Last modified: April 23, 2007