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This is a single-width IP module with sixteen channels of
buffered digital input/output.
The I/O signals are accessed as the top and bottom halves of one 16-bit
location. Each set of
eight signals can be selected to be inputs or outputs. At power-up or after
an IP reset, all signals
default to the input state.
A control register associated with the I/O register determines whether each
half will act as inputs
or outputs and for input mode also controls the way that inputs are sampled.
When output mode is selected, the output data reflects the last data written
to the corresponding
I/O register. The buffered TTL outputs exactly mirror the logical state of
the data written, thus
writing a ‘1’ to the register makes the TTL output signal go high.
When input mode is selected other control register bits come into play and
determine the
sampling mode of the register. One common sampling clock can be selected
from a choice of
four in the range 1KHz to 1MHz. Also, a common de-bounce clock can be chosen
from the
following choices: 100Hz, 200Hz, 500Hz and 1KHz or a divided down external
clock source.
Writing to the port when input mode is selected has no effect.
Reading the port when output mode is selected will read back the last data
written.
A further register associated with each port controls which bits may
generate an interrupt when
in input mode. [Again, this function has no effect when in output mode.]
All the above registers occupy I/O space on the IP card.
The full specification of the 8505 is available in
Adobe .pdf format |
