Hytec Electronics Ltd

IP-SC-8511

32-Channel Scaler Industry Pack

Product Description

The Hytec IP-SC-8511 is a double-width  Industry Pack that provides 32 channels of counting register with the following characteristics:-

32 independent channels
Full 24 bits binary count capacity
Each channel equipped with a transfer buffer register
Count rates from D.C. to 10MHz
32 bits Overflow register records overflow on each channel
TTL compatible inputs
Overall scaler inhibit control
Programmed internal/external Gate selection
Programmed selection of internally generated gate intervals
Gate interval accuracy +/-100ppm
Gate interval selection from 50ms/100ms/500ms/1s
Mode selection of transfer to buffer on read or at end of gate
Inputs via 8302 digital transition board and I/O connector
Inhibit via carrier board front panel socket

Specifications

 Size:                            Double width Industry Pack 3.6ins x 3.9 ins
Operating temp:             0 to 45 deg C ambient
Number of channels:      32
Max. count:                  24 bits plus overflow
Max count rate:             10MHz
Input levels:                   TTL compatible with high value pull-up        
Count control:               Overall inhibit via Strobe* input of data connector
                                   Overall gate with internal/external enable
Gate:                           Internal generation or external TTL input via I/O
Internal gate intervals:    Programmable 50ms/100ms/500ms/1s
Gate interval accuracy:  +/-100ppm
Inhibit & gate level:         TTL compatible with high value pull-up
Data format:                  Binary              
Power:                          +5V @ 200mA typical

Operating Modes

 There are three basic operating modes:-
1.       Transparent – the scaler contents are transferred to the buffer transfer register whenever it is read
2.       Command – the scaler contents are transferred to the buffer register when commanded to do so. This may be an on-the –fly operation or after the assertion of programmed disable.
3.       Gated – the scaler contents are transferred to the buffer register at the back edge of the gate interval and the scaler may be optionally cleared as determined by a bit in the CSR
Application Registers

 There are a number of application specific (I/O) registers; the CSR, the overflow status, the internal gate interval and the scaler transfer buffer registers.

CSR (IP address 0)

 EN        Enable the scalers to count when set to a logic 1.
EX        Enable the external gate when set to a logic 1
EI         Enable the internal gate action. when set to a logic 1.
T            Transparent mode. The scaler contents will be automatically transferred to the buffer registers when they are read.
CL        Clear the scalers at the end of the long interval. The scalers will be automatically transferred & cleared.
CS        Clear the scalers at the end of the short interval. The scalers will be automatically transferred & cleared
LE        Long interval interrupt enable. Enables interrupt at the end of the long interval.
SE        Short interval interrupt enable. Enables interrupt at the end of the short interval.
1s         Enable repeated 1 second long internal gate intervals.Initiated on EN. Terminated when EN is set to zero 500              Enable 500ms long internal gate intervals. Initiated and terminated by the setting of EN
100              Enable 100ms short internal gate intervals. Initiated and terminated by the setting of EN
50         Enable 50ms short internal gate intervals. Initiated and terminated by the setting of EN
L          Latch. The scalers are transferred to the buffer registers when a logic 1 is written to this bit
Inc            Increment all scalers when a logic 1 is written to this bit
LI         Long interval flag. Set when the long interval (500ms or 1s) has finished The flag is reset by writing a 0 to this bit.
SI         Short interval flag. Set when the short gate interval (50ms or 100ms) has finished. The flag is reset by writing a logic 0 to this bit.
Overflow Register (IP addresses 1&2)

 The overflow register contains the overflow latches which are set whenever the respective scaler overflows. This is a 32-bit register which is accessed as two 16-bit registers.The overflows are designated as O0-O31 for scalers 0 to 31.

Vector (IP address 4)

 Scaler Buffer Registers 0 to 31 (IP addresses 8-27)

 The scaler transfer buffer registers may be read at any time. They will hold the scaler data according to the mode set up in the CSR
The registers are 24 bits in length and the upper 8 bits are read from the upper of the two site data connectors in parallel with the 16 bits from the lower site.

 ID PROM

The ID data is stored in a serial EEPROM. The byte addresses are as below:-

00         ASCII            ‘VI’
02         ASCII            ‘TA’
04         ASCII            ‘4 ‘
06         Hytec ID high byte
08         Hytec ID low word
0a         Model number
0c         Revision
0e            Reserved
10         Driver ID
12         Driver ID
14         Flags (8MHz)
16         No of bytes used
18         Not used
Note: The access time of this data is approximately 5us per word.

 Operation

The internal or external gate can be used to repeatedly acquire counts for the duration of the gate interval and transfer them to the buffer register at the end of each interval with or without a scaler clearing action after the transfer.
The gate operation depends on the setting of the EX/EI and CL/CS bits of the CSR.
If EX is set then the external gate will cause the data to be transferred to the buffer registers and the scalers cleared at the end of the gate interval if either of the CL/CS bits are set. Otherwise the scalers may be transparently read or transferred on command (L).

When using the internal gate it is possible to set CL and enable both a short gate interval and a long interval.  The buffer register will be updated at the end of each short gate interval and then finally at the end of the long interval whereupon the scalers will be cleared ready for the next short/long gate interval.

 The end of the intervals can be detected by reading the CSR and testing for bits SI and LI which indicate the end of the short or long intervals. Interrupt can be generated by setting the corresponding SE and LE bits.

 The internal gate is derived from the 8MHz clock of the Carrier board and the system clock. It is therefore subject to the normal variation of crystal clock oscillators (up to +/-100ppm stability)

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Last modified: July 27, 2005