Hytec Electronics Ltd

Data Acquisition and Control

16-Channel 32bit Scaler Industry Pack IP-Scaler-8512  

Product Description

The Hytec IP-SC-8512 is a single-width  Industry Pack that provides 16  preset counting registers with the following characteristics:-

• 16 independent preset counting channels

• Full 32 bits binary count capacity per channel

• Adjacent counters may be daisy-chained to provide 64 bits

• Counters may be read whilst counting via shadow register

• Programmable preset limit on each channel

• Count rates from D.C. to 18MHz

• Arm register enables individual channels

• Overflow register provides status of all scalers

• Programmable disarm on overflow for each channel.

• Interval mode allows one scaler to control a group of scalers

• Maskable interrupt generated by each channel on overflow

• Programmable gate enable connects 10MHz clock to scaler input

• Hardware start/stop control via Strobe* signal

• External common ARM In /ARM Out signals

• Hardware inputs via  transition board and I/O connector

• Software test command increments scalers

• ID, manufacturer, model, revision history and serial number can be read

• Software Drivers are available including EPICS drivers.

Specifications

Operating Mode
There are three basic operating modes:-
1.       Scaler  - the scaler counts input pulses when gated and armed until it overflows
2.       Preset scaler – the scaler can be overwritten with a value. When gated on it can count from this value until it overflows.
3.       Timer – a scaler is preset and is then clocked by the internal (when the gate enable is set) or an external clock until IRQ is generated. The scalers follwing this defined interval timer are then disabled until their arm bits are re-enabled. Arm can be set by software or by the Start signal presented via Strobe*.

Application Registers

Control & Status Register (IP address 0)

Read/write register defines the vector V7-V0 reset control, start/stop and IRQ status

IRQ       Any IRQ which is set and masked on sets this status bit. Read only
R          Reset - writing a 1 to this bit resets the cards registers Write only
SS        Start/stop – the overall enable (Strobe*) status . Read only
EN        Hardware ARM all counters via ARM In. Read only 
T          Test. Writing a logic 1 increments all scalers by one. Write only

Arm Register (IP address 1)

Read/write register.

Any bit which is set arms the relevant scaler

 IRQ Register (IP address 2)

The overflow from each scaler is latched. When a bit is set it indicates overflow.  Cleared by writing 0 Read/write register.

 IRQ Mask Register (IP address 3)

Read/write register.

Any bit which is set allows an over/underflow on the respective channel to generate IRQ

 Disarm on IRQ Register (IP address 4)

Read/write register.

Any bit which is set allows the overflow to disarm the relevant scaler interval.

 Interval-enable Register (IP address 5)

Read/write register.

Any bit which is set defines that a scaler is used as an interval timer. Following scalers are controlled

 Daisy-chain Register (IP address 6)

Read/write register.

Any bit which is set allows an overflow on the respective channel to clock the next scaler

 Gate-enable Register (IP address 7)

Read/write register.

Any bit which is set enables the 10MHz clock to clock a specific scaler

Scaler Registers 0 to 15 (Memory addresses LSWord 00-1E, MSWord 01-1F)

The scaler registers may be read at memory addresses 00-1E(even) for the least significant words and 01-1F(odd) for the most significant words. The scaler value can be set by writing  to the appropriate address.