| Product Description The Hytec IP-SI-8515 is a single-width Industry Pack that provides 8 serial interface lines with the following characteristics:- - 8 independent RS-232 UART channels
64 byte Transmit and Receive FIFOs Transmit and Receive FIFO level counters Programmable Tx and Rx FIFO Trigger Levels Automatic RTS/CTS Flow Control Automatic Xon/Xoff Software Flow Control with Status Indication Programmable Data Rate with Prescaler Up to 6.25 Mbps Serial Data Rate Single Interrupt Output for all 8 UARTs Global Interrupt Source for all 8 UARTs Simultaneous UART channel initialisation
Specifications Size: Single width Industry Pack 1.8ins x 3.9 ins Operating temp: 0 to 45 deg C ambient Number of channels: 8 Max. baud rate: 921.6kbps with internal clock. Data format: Binary/ASCII Input/Output levels: RS-232 Internal clock: 14.7456MHz oscillator Clock accuracy: +/-100ppm (0.01%) Power: +5V @ 400mA typical
Software Drivers are available including
EPICS drivers.
 Operating Modes Application Registers There are a number of application specific (I/O) registers. Interrupt Register (IP address 0) Read/write register defines the vector V7-V0, Read only interrupt source U7-U0 | D15 | D14 | D13 | D12 | D11 | D10 | D09 | D08 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 | | V7 | V6 | V5 | V4 | V3 | V2 | V1 | V0 | U7 | U6 | U5 | U4 | U3 | U2 | U1 | U0 |
V0-7 Interrupt vector to be used during IACK U0-7 Any bit which is set indicates the interrupting UART Interrupt Source Registers 1-3 (IP address 1-3) Indicate the source of each interrupt from UART0 to 7 . Bits 8-15 are 0. Read only register.
| D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 |
| U50 | U42 | U41 | U40 | U32 | U31 | U30 | U22 | U21 | U20 | U12 | U11 | U10 | U02 | U01 | U00 | | | | | | | | | | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 | | | | | | | | | | U72 | U71 | U70 | U62 | U61 | U60 | U52 | U51 | Timer Control Register (IP address 4&5) Read/write register. CS-Clock Select S/R-Single/Retrigger SS-Start/Stop IE-Timer Interrupt Enable | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CS | S/R | SS | IE |
Timer Counter Register (IP address 6&7) Read/write register. Timer counter data register. | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 | | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
8x Mode Register (IP address 8) Read/write register. Logic 0 sets 16x sampling. Logic 1 sets 8x sampling | D15 | D14 | D13 | D12 | D11 | D10 | D09 | D08 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | U7 | U6 | U5 | U4 | U3 | U2 | U1 | U0 |
Reserved Register (IP address 9) Read only register. | D15 | D14 | D13 | D12 | D11 | D10 | D09 | D08 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Reset Register (IP address A). Resets are write only R0-7 reset UART0-7 | D15 | D14 | D13 | D12 | D11 | D10 | D09 | D08 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | R7 | R6 | R5 | R4 | R3 | R2 | R1 | R0 |
Sleep Register (IP address B) S0-7 set UART0-7 into sleep mode Read/write register. | D15 | D14 | D13 | D12 | D11 | D10 | D09 | D08 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | |
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