Features

• Operates as a CAMAC module to EUR4100E.
• Complies with CAMAC specification IEEE 583 and IEEE 595.
• Bit serial and byte serial modes at up to 5 megahertz.
• Internal Crystal controlled or variable frequency clock source, or external clock input with comprehensive dividing networks on the selected source.
• Separate buffers for incoming replies or demand messages.
• Lost Sync indication.
• 12 bit maskable LAM register with front panel display.
• Q-Scan mode.
• Reply timeout.
• Echo mode.
• Test message generator with facilities for forcing errors.
• Dump store for message analysis.
• Functionally compatible with the Kinetics 3992 SHD.
• Single or 64 word demand buffer, address selectable.

Product Description

The Hytec SHD992 is a two–wide CAMAC module which transmits and receives signals on the CAMAC serial highway. It fully complies with CAMAC specifications. Bit serial and byte serial ports for data and clock are provided for the transmission of command and the acceptance of reply and demand messages. All control functions are controlled via the dataway. Serial messages are initiated by loading command and data registers. All incoming messages are checked for both transverse and longitudinal parity. The serial clock can be controlled by a crystal source, variable frequency oscillator, or an external source. The internal oscillators may be divided down from sources of approximately one kilohertz to five megahertz. The external source may range from slow frequencies to a maximum of five megahertz. A twelve bit LAM status and LAM mask register set provide a comprehensive interrupt system. The LAM status register may be cleared or selectively cleared and the LAM mask register can be written, cleared, selectively set and selectively cleared. The mask and all control registers are cleared at power up or by a ’Z’ command.

Operational Features

Six registers provide communication between the Dataway and the Serial Highway Message transmission is initiated by:

• Writing the Command register with a serial Read or Command function, or
• Writing the Write Data register while the Command register contains a serial Write function.

Q-Mode

If the MR–bits is true in the Command register, an F(0).A(0) command to the module initiates another serial transmission. The serial Command message is the same as the previous message if the MQ–bit = 0. If MQ = 1, the new serial message has SA incremented if the previous SQ was true or SA reset and SN incremented if the previ-ous SQ was false. If the N–counter advances beyond N = 24 in this mode, the crate address is cleared. A subsequent transmission with CRATE = 0 will cause the ADNR (address not recognised) bit in the LAM register to be set upon receipt of the reply message.

Timeout

If 350 msec elapses between the start of a message transmission and receipt of a reply message (or unrecognised command message) the TIMEOUT signal is as-serted, which sets to the TMO LAM source. SHR also becomes true (SHR = RPL + TIMEOUT) and the RDY LAM source is set if/when CMD is true. Reply messages received after TIMEOUT is asserted are ignored.