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VMEBUS MADC 2508
The MADC 2508 is a dual height (6U) single width VME module which digitises 32 differential or 64 single–ended voltage signals with 16 bits resolution. Digitised values are stored in a 128K word memory. Scans of a programmed number of inputs are triggered either at programmed rates from 100kHz down to 10Hz, by hardware handshake or by soft trigger. The ADC has a good linearity and the ability to wait for amplifier settling times, according to programmed gain settings, before digitising commences.
Use of Address Modifiers
AM29 - Access configuration registers.
The 128k x 16 bit SRAM is located in extended (a32) address space. The memory offset is set by the value stored in the memory offset configuration register bits 2–15.
The configuration registers occupy 64 bytes in the short address space above the base address which is determined by printed circuit
board address jumpers. These are mapped as follows:–
BA+3E Channel 32 Descriptor Channel 31 Descriptor Read/Write
BA+22 Channel 4 Descriptor Channel 3 Descriptor Read/Write
BA+20 Channel 2 Descriptor Channel 1 Descriptor Read/Write
BA+16 Trigger Rate Read/Write
BA+14 Number of Scans to Trigger Read/Write
BA+10 CA Pointer MS Read/Write
BA+0E CA Pointer LS Read/Write
BA+0A Channels per scan Read/Write
BA+08 Memory attributes Read
BA+06 Memory offset Read/Write
BA+04 Control & status Read/Write
BA+02 Device type Read
BA+00 Identifier/Vector Read/Write
DB8 Gain 1
DB1 DB9 Gain 2
DB2 DB10 Gain 3
DB3 DB11 Filter Enable
DB4 DB12 Delay 1) 0=0S 1=2S
DB5 DB13 Delay 2) 2=4S 3=8S
DB6 DB14 Unipolar/Bipolar
DB7 DB15 +/–
D3–D0 A 4–bit code which defines the rate from 10Hz to 100kHz. Code 0 selects external/soft trigger. Code 15 disables trigger.
Number of Scans
DB15–DB0 A 16–bit value which sets the number of scans before interrupt.
DB0 - DB3 Most significant bits of the Address.
DB0 - DB15 Least significant bit of the Conversion Address.
DB15–DB0 The least significant 16bits of the Block Transfer Address Pointer.
DB15–DB0 An 8 or 16–bit value determines the interrupt vector value.
Channels per scan
DB7–DB0 Values of 1 to 64 determine the number of channels to be scanned.
DB15 and DB14 are asserted as a 1 to indicate
DB13 is asserted as a 1 to indicate accessibility is both non–privileged and supervisory.
DB12 is asserted as 0 to indicate block transfer capability.
DB11 is asserted as a 1 to indicate non–protected mode.
DB10, DB9 are asserted as 0 and DB8 is asserted as a 1 to indicate 50–99ns speed.
DB7–0 are asserted as 1s.
DB15 to DB2 determine the memory offset mapped
onto A31 to A18.
DB1 and DB0 are not used.
Control and Status
DB15 Scan done. Selected number of scans
DB13 12 bit conversion data when set to 1. Default 16 bits.
DB12 Loop back to zero at end of scan.
DB11 Differential mode enable when set to 1.
DB10 Connect reference to the input when set to 1.
DB9 Soft trigger. Trigger preset number of scans.
DB8 ARM enables acquisition when set to 1.
DB7 Interrupt enable when 1.
DB6 Memory full. Interrupt if enabled.
DB5 Single scan. When set to 1 a single scan is enabled for each trigger.
DB3 ) Three bits set interrupt priority level.
DB1 Logic 1. The module does not drive Sysfail.
DB0 Writing a 1 resets the module. Reading a 1 means that acquisition is occurring.
DB11–DB0 define the device code = 2508.
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Post : 5 Cradock Road, Reading, Berkshire, RG2 0JT, England.
Phone : +44 (0)118 9757770
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