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IP-ADC-8403 is a single-width Industry Pack that provides 8 channels of simultaneously sampled analogue to digital conversion
Description
1. Overall
Two 24 bit ADCs
Each ADC multiplexer has 4 differential or 8 pseudo-differential inputs
On-chip ADC temperature sensors
Open-circuit and short-circuit input detection
Programmable current sources for excitation
Programmable gain amplifiers provide gains from 1 to 128
Programmable offset DACs allow input to amplifier to be offset to 1/2 FSR
Programmable self-calibration.
Fast settling and sinc notch filters for interference rejection
Front-end isolated to 100V when used with DC-DC Converters
Choice of straight-through or filtered transition board with excitation options
2. Product Specification
Size: Single width Industry Pack 1.8ins x 3.9 ins
Operating temp: 0 to 45 deg C ambient
Power: +5V @ 300mA typical, +12V @ 100mA, -12V @ 10mA typical
Isolation: 100V (external power) ISOGND-VMEGND
2.1 ADC
Number of channels: 8 differential /16 pseudo-differential inputs plus Common
Input voltage range: +/-2.5V with respect to Common or another input in the range 0V to +5V
Resolution: Up to 22 bits dependent on ADC setup
No missing codes: 24 bits
Conversion time per channel: Depending on clock, decimation values (set by ADC sample rate) and number of channels sampled e.g.8 channels at an ADC sample of 200Hz = 100ms/chan
Int. Non-linearity +/-0.0015% of full scale max.
Offset : 7.5ppm of full scale range typical
Offset drift: 0.02 ppm per deg C typical
Gain error: +/-0.05% of full scale range (+/-0.002% with calibration factor)
Gain error drift: 0.5 ppm per deg C typical
Bandwidth: 10Hz to -3dB
Throughput: 100 conversions per sec max with ext clock
Noise: 10uV r.m.s.
Distortion: -105dB for 1kHz input
CMRR: -100dB
CMV: +5V, -0.2V with respect to ISOGND
Data format: Binary
Memory: 512K x 32 bits (32K samples per channel).
IDAC
Number of channels 2
Full-scale current 0.5mA (range 1), 1mA (range 2), 2mA (range 3)
Short circuit duration Indefinite
Resolution 8 bits
Monotonicity 8 bits
INL +/-0.4LSB typical
DNL +0.4/-0.1 LSB typical
Compliance voltage +4V
Absolute Error 5%
Offset Drift +/- 2 ppm/deg C typical
Gain Drift +/-125ppm/deg C typical
Vref Out
Number of outputs 2
Voltage +2.5V
Error +/-0.05% max
Drift 1ppm/degC max.
Current available 10mA min.
3. Operating Modes
3.1 Scanning
There are three operating modes:-
1. DC sampling - when the 8403 is armed the inputs are scanned and logged to memory and channel registers hold the last ADC reading. This will cause an interrupt when the memory is full and will wrap around until halted by the user.
2. Triggered sampling - as above but where the inputs are scanned for a programmed number of scans as entered in to the NCO register.
3. User controlled - Here the user controls the ADC.
3.2 Excitation
Three excitation signal types are available:-
1. +5V regulated output derived from the +12V (as selected from external or VME supplies)
2. Two +2.5V buffered Vref outputs
3. Two 8 bit programmable IDAC outputs.
An isolated digital calibration enable (/CALEN) signal can be generated by command for switching calibration voltages.
3.3 Sampling Clock
On-chip, programmed or external sampling clocks may be selected according to filter and conversion rate requirements. The conversion rate and the filtering are setup using the on board registers of the ADC ICs.
4. Memory Map
The memory is used to record ADC data.
4.1 Conversion Memory
The conversion memory contains 512k samples of 32 bits each.
These are each divided into sixteen segments allocated to conversions from ADC A chan 1 to chan 8 and ADC B chan 1 to chan 8 .
When the memory is full the Full Flag status is set.
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