VME provides a modular means to implement computer-independent systems for real-time data capture, industrial processing, instrumentation, automation and communications for use in Science, Offices, and Industry.

VME grew out of the earlier Versabus standard devised by Motorola, differing both in the Hardware - Eurocard rather than Motorola special - and in what rnicroprocessors it supported - any, up to 32 bits wide rather than the 16-bit Motorola 68000. When VMEbus was first defined, in the the early 'eighties, Eurocard had been established in Europe for many years, and has a much more resilient pin-and-socket connector than the older printed edge connector. The definitive VME specification is IEEE1014-1987, IEC821. It must be emphasised that this is a muti-supplier product, which cannot be made obsolete, as so easily happens with single-supplier products. Indeed there are now over 200 VME manufacturers in existence and literally thousands of products; all compatible!

VMEbus has a 32-bit address bus (up to 4 gigabytes of addressable memory), a 32-bit data bus, and can handle data transfers at speeds in excess of 40 Mbytes/sec. It uses a 'Master-Slave' architecture and many Masters can reside on the bus - it is a Multiprocessing Bus. Selection of the next Master to take control of the bus is done by a Central Arbiter, which also handles the seven levels of interrupt which are supported. There are four buses altogether: The Data Transfer Bus, The Arbitration Bus, The Priority interrupt Bus and The Utility Bus which carries generic signals like a 16-MHz clock and Power-up Reset. Masters, Slaves and the Central Arbiter are all plugged into the 'sub-rack' or crate which may have one Backplane (for 24 address bits and 16 data bits) or Two (32 address bits and 32 data bits, with extra power and some user-defined pins; P1/J1 at the top and P2/J2 at the bottom) or even three or four, although these are not currently defined in the IEEE1014-1987, specification.


VME64 represents an extension to the VME specification permitting 64-bit data handling. The enhanced operation provided by VME64 is summarised below:

  • Includes all capabilities described in VMEbus Rev C.1 specification
  • For faster and wider transfers adds the multiplexed block transfer (MBLT) feature. This uses both the data and address lines in the same basic asynchronous protocol as D08(EO), D16 and D32 transfers to achieve D64 data transfers.
  • 64-bit addressing mode added
  • 40-bit addressing mode added for J1/P1-only systems. A multiplexed data cycle (MD32) has been added to allow 32 bit transfers on P1 only using the data bus and address bus for 32 bit transfers.
  • A40BLT block transfer mode allows 8, 16 and 32 bit transfers for J1/P1 only systems (and P1/P2)
  • 5 lock commands added to provide resource locking
  • Configuration ROM and Control & Status Registers (CR/CSR) defined. The need for jumpered selection of address is eliminated
  • Single (address with data) or double phase (address followed by data) cycles. For D08(E), D08(O), D16,D32 and MD32 reads there is an address broadcast phase followed by a data phase with a single data transfer. In BLT, (except for the first write cycle), MBLT and A40BLT cycles there is an address broadcast phase followed by a data phase followed by multiple data transfers. All A40 And A64 transfers have two phases.
  • Address modifiers for lock and A40/A64 block commands have been added

With the introduction of VME64x (VME Extensions) user defined I/O connections are now available through a rear VME64x backplane. Before the introduction most of the user defined I/O was brought out through the front panel. The detailed enhancements are as follows:-

  • P1/J1 and P2/J2 connectors increased to 160 pins per connector by the addition of ‘z’ and ‘d’ rows
  • Optional P0/J0 95-way 2mm metric connector with 19 or 38 shield pins
  • Supply voltages of +3.3V and auxiliary volts plus more +5V power
  • 35 extra ground returns between board and backplane
  • 46 extra user defined I/O pins on the P2/J2 connector
  • 14 bussed spare pins and associated backplane lines plus 2 spare unbussed spare pins on the J1/P1 connector for future definition
  • Pins allocated for a test and maintenance bus
  • Slot geographical addressing
  • Mechanical support for EMC control
  • Mechanical support for ESD control
  • Solder side covers with ESD protection
  • Injection/extraction handles with a locking feature
  • User installed board to slot keying
  • Alignment pin which supports solid keying, improved connector alignment, front panel ESD protection and EMC gasket alignment
  • Front panel safety ground
  • Reserved area on the front panel for attachment of ID and/or bar code labels
  • Rear I/O transition boards
  • Added CR/CSR definition
  • Supporting specifications for hot swap
  • 2eVME fast 2 edge protocol