Hytec Electronics Ltd.

An introduction to the VME64x specification

An exciting new range of Analogue and Digital I/O modules for data acquisition and control.



Fully Hot-Swap capable with auto power-up and full EMC shielding.

Together with Industry Packs (IP) for extra functionality in a very compact form. The rapidly expanding range includes 8-channel ADC, 16-channel DAC, 32-channel Scaler.

Industry Pack Cards (IP) - ADC, DAC or Scaler



For a  listing of all VME64x modules available,

An Introduction

VMEbus has a 32-bit address bus (up to 4 gigabytes of addressable memory), a 32-bit data bus, and can handle data transfers at speeds in excess of 40 Mbytes/sec. It uses a 'Master-Slave' architecture and many Masters can reside on the bus - it is a Multiprocessing Bus. Selection of the next Master to take control of the bus is done by a Central Arbiter, which also handles the seven levels of interrupt which are supported. There are four buses altogether: The Data Transfer Bus, The Arbitration Bus, The Priority interrupt Bus and The Utility Bus which carries generic signals like a 16-MHz clock and Power-up Reset. Masters, Slaves and the Central Arbiter are all plugged into the 'sub-rack' or crate which may have one Backplane (for 24 address bits and 16 data bits) or Two (32 address bits and 32 data bits, with extra power and some user-defined pins; P1/J1 at the top and P2/J2 at the bottom) or even three or four, although these are not currently defined in the IEEE1014-1987, specification. View Hytec's VME range.

VME64

• Includes all capabilities described in VMEbus Rev C.1 specification
• For faster and wider transfers adds the multiplexed block transfer (MBLT) feature. This uses both the data and address lines in the same basic asynchronous protocol as D08(EO), D16 and D32 transfers to achieve D64 data transfers.
• 64-bit addressing mode added
• 40-bit addressing mode added for J1/P1-only systems. A multiplexed data cycle (MD32) has been added to allow 32 bit transfers on P1 only using the data bus and address bus for 32 bit transfers.

• A40BLT block transfer mode allows 8, 16 and 32 bit transfers for J1/P1 only systems (and P1/P2)
• 5 lock commands added to provide resource locking
• Configuration ROM and Control & Status Registers (CR/CSR) defined. The need for jumpered selection of address is eliminated
• Single (address with data) or double phase (address followed by data) cycles. For D08(E), D08(O), D16,D32 and MD32 reads there is an address broadcast phase followed by a data phase with a single data transfer. In BLT, (except for the first write cycle), MBLT and A40BLT cycles there is an address broadcast phase followed by a data phase followed by multiple data transfers. All A40 And A64 transfers have two phases.
• Address modifiers for lock and A40/A64 block commands have been added

 VME64x

• P1/J1 and P2/J2 connectors increased to 160 pins per connector by the addition of ‘z’ and ‘d’ rows
• Optional P0/J0 95-way 2mm metric connector with 19 or 38 shield pins
• Supply voltages of +3.3V and auxiliary volts plus more +5V power
• 35 extra ground returns between board and backplane
• 46 extra user defined I/O pins on the P2/J2 connector
• 14 bussed spare pins and associated backplane lines plus 2 spare unbussed spare pins on the J1/P1 connector for future definition
• Pins allocated for a test and maintenance bus
• J1/P1 connector for future definition